Trends in recent years of higher speeds and greater information volumes have led to increasingly higher technical requirements for electronic devices such as downscaling and increasing frequencies. As a result, requirements to increase the electrostatic discharge (ESD) immunity of electronic devices have abruptly increased as well. Also, in small high-speed switching devices used in portable devices, etc., and MOS transistors widely used in voltage converter circuits, etc., downscaling the device or reducing the gate oxide film thickness causes concern about reduced ESD immunity.
In such devices, ESD protection diodes are often formed simultaneously on the silicon substrate. In particular, protection elements using polycrystalline silicon have high degrees of freedom during the device manufacturing processes and are widely used.
Because conventional ESD protection diodes are provided in a ring-like closed annular structure, the surface area of the central portion is an ineffective surface area. Therefore, in the case where the junction surface area of a protection diode is increased to obtain a high ESD immunity, the ineffective surface area increases and the surface area of the entire device increases.
Therefore, there have been proposals to provide a high breakdown-voltage protection diode by connecting a ring-like protection diode formed in a chip peripheral portion and the like to a ring-like protection diode formed in a peripheral portion of an electrode pad.